參數(shù)資料
型號: MC33397
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control(帶SPI和并口輸入控制的2或6低端開關(guān))
中文描述: 雙/六角低側(cè)開關(guān)SPI和并行輸入控制(帶的SPI和并口輸入控制的2或6低端開關(guān))
文件頁數(shù): 7/20頁
文件大?。?/td> 562K
代理商: MC33397
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33397
7
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V
V
DD
5.25 V, -40
°
C
T
A
125
°
C, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUT TIMING
Output Rise Time
V
PWR
=14 V, R
LOAD
=25
, 20–80%
t
R
1.0
1.2
10
μ
s
Output Fall Time
V
PWR
=14 V, R
LOAD
=25
, 80–20%
t
F
1.0
2.0
10
μ
s
Output Turn-On Propagation Delay
t
PON
1.0
4.0
10
μ
s
Output Turn-Off Propagation Delay
t
POFF
1.0
4.0
10
μ
s
FAULT TIMING
Output Short-to-Battery Fault Filter Time
t
SS
30
50
90
μ
s
Output Refresh Timer
t
REF
3.0
4.1
6.0
ms
Output Refresh Timer Duty Cycle
D
0.2
1.56
3.0
%
Output Off-State Open Circuit Fault Filter Time
t
OOF
30
50
90
μ
s
SPI/MISCELLANEOUS TIMING
SO Disable Time (10 K Pull-Up Resistor on SO)
CS=0.8 V to SO > 0.8*V
DD
t
SODIS
80
110
ns
SO Enable Time (10 K Pull-Up Resistor on SO)
CS=0.8 V to SO Low Impedance
t
SOEN
80
110
ns
SO Rise Time
CL < 200 pF
t
SORISE
30
50
ns
SO Fall Time
CL < 200 pF
t
SOFALL
30
50
ns
SO Valid Time
Falling Edge of SCLK to SO Valid
t
VALID
65
80
ns
Required Time Between Falling Edge of CS to Rising Edge of
SCLK
t
LEAD
100
140
ns
Required TIme Between Rising Edge of CS to Falling Edge of
SCLK
t
LAG
0
50
ns
Required Time Between SI to Rising Edge of SCLK
t
SU
25
45
ns
POR/
EN
Wake-Up Timer
t
POR
20
40
60
μ
s
Mode Change Timer (P2)
t
MODE
5.0
10
25
μ
s
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
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MC33397DW 制造商:Freescale Semiconductor 功能描述:Dual/Hex Low-Side Switch with Both SPI and Parallel Input Control
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