LOGIC COMMANDS AND REGISTERS Wake-up Input " />
參數(shù)資料
型號(hào)： MC33989DW
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 30/72頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASE W/CAN 28-SOIC
標(biāo)準(zhǔn)包裝： 26
控制器類型： 系統(tǒng)基礎(chǔ)芯片
接口： CAN
電源電壓： 5.5 V ~ 18 V
電流 - 電源： 45mA
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
配用： KIT33989DWEVB-ND - KIT EVAL 33989DW HS SBC
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Wake-up Input Register (WUR)
The local wake-up inputs, L0, L1, L2, and L3 can be used in both Normal and Standby modes as port expander, as well as
and for waking up the SBC in Sleep or Stop modes. See Table 22.
The wake-up inputs can be configured separately, while L0 and L1 are configured together. Bits L2 and L3 are configured
together. See Table 23.
Table 24 provides Status bits data.
Timing Register (TIM1/2)
This register is composed of two registers:
1. TIM1–controls the watchdog timing selection as well as the window or timeout option. TIM1 is selected when bit D3 is 0.
Please see Table 25.
2. TIM2–is used to define the timing for the cyclic sense and forced wake-up function. TIM2 is selected when bit D3 is read
operation it is not allowed in either TIM1 or TIM2 registers. Please see Table 27.
Table 22. WUR Register
WUR
D3
D2
D1
D0
$100B
W
LCTR3
LCTR2
LCTR1
LCTR0
R
L3WU
L2WU
L1WU
L0WU
Reset Value
0
Reset Condition
POR, NR2R, N2R, STB2R, STO2R
Table 23. WUR Control Bits
LCTR3
LCTR2
LCTR1
LCTR0
L0/L1 Config
L2/L3 Config
x
0
Inputs Disabled
—
x
0
1
High Level Sensitive
x
1
0
Low Level Sensitive
x
1
Both Level Sensitive
0
x
—
Inputs Disabled
0
1
x
High Level Sensitive
1
0
x
Low Level Sensitive
1
x
Both Level Sensitive
Table 24. WUR Status Bits
Status Bit
Description
L3WU
Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes)
L2WU
L1WU
L0WU
Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2
input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above
threshold, 0 means that LX input is below threshold).
If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur
only if SBC was in Stop mode.
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