SUPPLEMENTAL APPLICATION NOTES Figure 46. Node is " />
參數資料
型號: MC33989DW
廠商: Freescale Semiconductor
文件頁數: 54/72頁
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 28-SOIC
標準包裝: 26
控制器類型: 系統(tǒng)基礎芯片
接口: CAN
電源電壓: 5.5 V ~ 18 V
電流 - 電源: 45mA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC W
包裝: 管件
配用: KIT33989DWEVB-ND - KIT EVAL 33989DW HS SBC
Analog Integrated Circuit Device Data
58
Freescale Semiconductor
33989
TYPICAL APPLICATIONS
SUPPLEMENTAL APPLICATION NOTES
Figure 46. Node is in Bus Off State
SOFTWARE ASPECTS
Introduction
This section describes the MC33989 operation and the microcontroller SPI software routine that has to be executed in order
to control the device. Structure of the Byte: ADR (3 bits) + R/W (1bit) + DATA (4 bits). MSB is sent first. Refer to MC33989
specifications for more details.
How to Enter in Normal Mode After a Power-Up
Figure 47. Normal Mode After Power-up
The DC current can be calculated as follows:
Idc= (Time in dominant * peak current of the fault) / total error frame time
Idc= (17+15)*peak current / ((23*15)+1408)=32 / 1753*peak current
Example for CANL2Vbat (peak current = - 240 mA): Idc = 32*(-) 240 / 1753=(-)4.38 mA
TX
RX
Rx is driven only during the glitch occuring on the CAN bus (the dominant time is shorter than a bit time)
TEC=128: the node reaches the error passive level
23 recessive bits: CAN passive error frame
Node sends one dominant bit. As there is still the fault, the TEC is incremented by 8 each time.
128 occurrences of 11 recessive bits
BUS OFF is recover
TEC reaches 255: the node is BUS OFF
read LX wake-up flag
Write watchdog
X is the period of the watchdog ex:$00 for 10 ms
Clear V2low, Vsuplow flags
Clear Batfail, Gfail,Wdrst flags
read CAN/WU flag
ALL FLAGS ARE READ
Write watchdog
X is the period of the watchdog ex $00 for 10 ms
note:this register has to be refreshed before the end of the watchdog
period
Power-up
Reset
Normal request
Normal
Read IOR ($60)
Read MCR ($00)
Read CAN ($40)
Write TIM1= $BX
Read WUR ($80)
Write TIM1 =$BX
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