參數(shù)資料
型號(hào)： MC56F8025MLD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 12/161頁
文件大?。?/td> 2160K
代理商： MC56F8025MLD
Resets
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
109
default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues
to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz
system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables
the device and minimizes its power utilization but is only recoverable via reset.
When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be
put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.
All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system
clock for PWM, Timers, and I2C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of
operation is 32MHz.
6.6 Resets
The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the
external reset pin and the Power-On Reset (POR). The three synchronous sources are the software reset
(SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1,
the COP time-out reset (COP_TOR), and the COP loss-of-reference reset (COP_LOR). The reset
generation module has three reset detectors, which resolve into four primary resets. These are outlined in
Table 6-3. The JTAG circuitry is reset by the Power-On Reset.
Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks
use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset.
Table 6-3 Primary System Resets
Reset Sources
Reset Signal
POR
External
Software
COP
Comments
EXTENDED_POR
X
Stretched version of POR released 64
OSC_CLK cycles after POR deasserts
CLKGEN_RST
XXXX
Released 32 OSC_CLK cycles after all reset
sources, including EXTENDED_POR, have
released
PERIP_RST
XXXX
Releases 32 SYS_CLK cycles after the
CLKGEN_RST is released
CORE_RST
XXXX
Releases 32 SYS_CLK cycles after
PERIP_RST is released
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC56F8027VLD 制造商:Freescale Semiconductor 功能描述:
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