參數(shù)資料
型號: MC56F8025MLD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 155/161頁
文件大小: 2160K
代理商: MC56F8025MLD
Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
93
6.3.12
Stop Disable Register 1 (SD1)
See Section 6.3.11 for general information about Stop Disable Registers.
Figure 6-13 Stop Disable Register 1 (SD1)
6.3.12.1
Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.12.2
Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.3
Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.4
Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.5
Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
6.3.12.6
Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.7
Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
Base + $F
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PIT2_
SD
PIT1_
SD
PIT0_
SD
0
TA3_
SD
TA2_
SD
TA1_
SD
TA0_
SD
Write
RESET
00
0
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參數(shù)描述
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