參數(shù)資料
型號: MC56F8025MLD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 137/161頁
文件大?。?/td> 2160K
代理商: MC56F8025MLD
Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
77
5.6.18
IRQ Pending Register 3 (IRQP3)
Figure 5-20 IRQ Pending Register 3 (IRQP3)
5.6.18.1
IRQ Pending (PENDING)—Bits 63–49
These register bit values represent the pending IRQs for interrupt vector numbers 49 through 63.
Ascending IRQ numbers correspond to ascending bit locations.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.19
Interrupt Control Register (ICTRL)
Figure 5-21 Interrupt Control Register (ICTRL)
5.6.19.1
Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.19.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
Base + $11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PENDING[63:49]
Write
RESET
11111
1111111
1111
$Base + $16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
INT
IPIC
VAB
INT_
DIS
1
0
Write
RESET
00000
0000001
1100
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