參數(shù)資料
型號： MC56F8025MLD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 48/161頁
文件大?。?/td> 2160K
代理商： MC56F8025MLD
Inter-Integrated Circuit Interface (I2C) Timing
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
141
10.12 Inter-Integrated Circuit Interface (I2C) Timing
Table 10-17 I2C Timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0100
0400
kHz
Hold time (repeated)
START condition. After
this period, the first clock
pulse is generated.
tHD; STA
4.0
—
0.6
—
μs
LOW period of the SCL
clock
tLOW
4.7
—
1.23
—
μs
HIGH period of the SCL
clock
tHIGH
4.0
—
0.6
—
μs
Set-up time for a repeated
START condition
tSU; STA
4.7
—
0.6
—
μs
Data hold time for I2C bus
devices
tHD; DAT
01
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.452
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
01
0.92
μs
Data set-up time
tSU; DAT
2503
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
—
1003, 4
4. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT > = 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
trmax + tSU; DAT = 1000 + 250 = 1250ns (according to the Standard mode I
2C bus specification) before the SCL line is
released.
—ns
Rise time of both SDA and
SCL signals
tr
—
1000
20 +0.1Cb
5
5. Cb = total capacitance of the one bus line in pF
300
ns
Fall time of both SDA and
SCL signals
tf
—300
20 +0.1Cb
5
300
ns
Set-up time for STOP
condition
tSU; STO
4.0
—
0.6
—
μs
Bus free time between
STOP and START
condition
tBUF
4.7
—
1.3
—
μs
Pulse width of spikes that
must be suppressed by
the input filter
tSP
N/A
0
50
ns
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參數(shù)描述
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MC56F8027VLD 制造商:Freescale Semiconductor 功能描述:
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