參數(shù)資料
型號: MC56F8323MFB60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 120 MHz, OTHER DSP, PQFP64
封裝: PLASTIC, LQFP-64
文件頁數(shù): 21/140頁
文件大?。?/td> 741K
代理商: MC56F8323MFB60
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
117
Preliminary
Figure 10-4 Frequency versus Temperature
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
16T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
ns
tIG - FAST
14T
IRQA Width Assertion to Recover from Stop State3
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
ns
Fr
eq
uen
cy
in
MHz
Temperature
- 50
- 30
- 10
+ 10
+ 30
+ 50
+ 70
+ 90
+ 110
+ 130
+ 150
7.5
7.6
7.7
7.9
7.8
8.0
8.1
8.2
Typical Response
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