Peripheral Memory Mapped Registers
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
51
Preliminary
Table 4-25 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym
Address Offset
Register Description
LVI_CONTROL
$0
Control Register
LVI_STATUS
$1
Status Register
Table 4-26 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
FMCLKD
$0
Clock Divider Register
FMMCR
$1
Module Control Register
Reserved
FMSECH
$3
Security High Half Register
FMSECL
$4
Security Low Half Register
Reserved
FMPROT
$10
Protection Register (Banked)
FMPROTB
$11
Protection Boot Register (Banked)
Reserved
FMUSTAT
$13
User Status Register (Banked)
FMCMD
$14
Command Register (Banked)
Reserved
FMOPT 0
$1A
16-Bit Information Option Register 0
Hot temperature ADC reading of Temperature Sensor;
value set during factory test
FMOPT 1
$1B
16-Bit Information Option Register 1
Trim cap setting of the relaxation oscillator
FMOPT 2
$1C
16-Bit Information Option Register 2
Room temperature ADC reading of Temperature Sensor;
value set during factory test