參數(shù)資料
型號: MC56F8346VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 10/160頁
文件大?。?/td> 1415K
代理商: MC56F8346VFV60
10
56F8346 Technical Data
Preliminary
1.5 Product Documentation
The documents in
Table 1-2
are required for a complete description and proper design with the
56F8346. Documentation is available from local Motorola distributors, Motorola semiconductor
sales offices, Motorola Literature Distribution Centers, or online at
http://www.motorola.com/semiconductors
.
Table 1-2 56F8346 Chip Documentation
Table 1-1 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0]
cdbw[15:0]
Program data bus for instruction word fetches or read operations.
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
pab[20:0]
cdbr_m[31:0]
cdbw[31:0]
xab1[23:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes
1
, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
1.
Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E family architecture,
and 16-bit hybrid controller core processor and the
instruction set
DSP56800ERM/D
568300 Peripheral User
Manual
Detailed description of peripherals of the 56F8300
devices
MC56F8300UM/D
56F8300 SCI/CAN
Bootloader User Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
MC56F83xxBLUM/D
56F8346
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
MC56F8346/D
56F8346
Product Brief
Summary description and block diagram of the
56F8346 core, memory, peripherals and interfaces
MC56F8346PB/D
56F8346
Errata
Details any chip issues that might be present
MC56F8346E/D
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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參數(shù)描述
MC56F8346VFVE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8346VFVER2 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8347 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8347MPY60 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-BIT HYBRID CONTROLLERS
MC56F8347MPYE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT