參數(shù)資料
型號(hào): MC56F8346VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 101/160頁
文件大?。?/td> 1415K
代理商: MC56F8346VFV60
Register Descriptions
56F8346 Technical Data
Preliminary
101
6.5.1.4
Stop Disable (STOP_DISABLE)—Bits 3–2
00 - STOP mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then
only be changed by resetting the device
11 - Same operation as 10
6.5.1.5
Wait Disable (WAIT_DISABLE)—Bits 1–0
00 - WAIT mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
10 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then
only be changed by resetting the device
11 - Same operation as 10
6.5.2
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset
(POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software
should clear this register.
SIM Reset Status Register (SIM_RSTSTS)
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–6
6.5.2.2
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to
SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by
software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
Software Reset (SWR)—Bit 5
6.5.2.3
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit
position will set the bit, while writing a 1 to the bit will clear it.
COP Reset (COPR)—Bit 4
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
O
0
0
0
0
0
0
0
SWR
COPR
EXTR
POR
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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