參數(shù)資料
型號: MC56F8346VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 107/160頁
文件大?。?/td> 1415K
代理商: MC56F8346VFV60
Register Descriptions
56F8346 Technical Data
Preliminary
107
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–4
6.5.8.2
This bit selects the alternate function for GPIOC3.
GPIO C3 (C3)—Bit 3
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register
in the
56F8300 Peripheral User Manual
)
1 = SS1
6.5.8.3
This bit selects the alternate function for GPIOC2.
GPIO C2 (C2)—Bit 2
0 = INDEX1/TB2 (default)
1 = MISO1
Table 6-2 Control of Pads Using SIM_GPS Control
1
1.
bits is used for each pin.
This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control
Pin Function
Control Registers
Comments
G
G
S
Q
S
O
GPIO Input
0
0
GPIO Output
0
1
Quad Timer Input /
Quad Decoder
Input
2
2.
Reset configuration
1
0
0
See the “Switch Matrix for Inputs to the Timer”
table in the
56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.
Quad Timer
Output / Quad
Decoder Input
3
3.
Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
1
0
1
SPI input
1
1
See SPI controls for determining the direction
of each of the SPI pins.
SPI output
1
1
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
0
0
C3
C2
C1
C0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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