參數(shù)資料
型號: MC56F8346VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 100/160頁
文件大?。?/td> 1415K
代理商: MC56F8346VFV60
100
56F8346 Technical Data
Preliminary
6.5.1
SIM Control Register (SIM_CONTROL)
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–6
6.5.1.2
OnCE Enable (OnCE EBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.3
This bit is always read as 0. Writing a 1 to this field will cause the part to reset.
Software Reset (SWRST)—Bit 4
Add.
Offset
Register
Name
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
$0
SIM_
CONTROL
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
$1
SIM_
RSTSTS
0
0
0
0
0
0
0
0
0
0
SWR
COPR EXTR
POR
0
0
$2
SIM_SCR0
FIELD
$3
SIM_SCR1
FIELD
$4
SIM_SCR2
FIELD
$5
SIM_SCR3
FIELD
$6
SIM_MSH_
ID
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
$7
SIM_LSH_ID
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
$8
SIM_PUDR
0
PWMA
1
CAN
EMI_
IRQ
XBOOT PWMB
PWMA
0
0
CTRL
0
JTAG
0
0
0
Reserved
$A
SIM_
CLKOSR
R
W
R
W
R
W
R
W
R
W
0
0
0
0
0
0
A23
A22
A21
A20
CLKDIS
CLKOSEL
$B
SIM_GPS
0
0
0
0
0
0
0
0
0
0
0
0
C3
C2
C1
C0
$C
SIM_PCE
EMI
ADCB
ADCA
CAN
DEC1
DEC0
TMRD
TMRC
TMRB
TMRA
SCI1
SCI0
SPI1
SPI0
PWM
B
PWM
A
$D
SIM_ISALH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ISAL[23:22]
$E
SIM_ISALL
ISAL[21:6]
= Reserved
Figure 6-2 SIM Register Map Summary
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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