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| 型號(hào)： | MC68307PU16V |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 186/264頁(yè) |
| 文件大小： | 949K |
| 代理商： | MC68307PU16V |
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Signal Description
MOTOROLA
MC68307 USER’S MANUAL
2-5
2.1 BUS SIGNALS
The following signals are used for the MC68307 bus.
2.1.1 Address Bus (A23–A0)
The address bus signals are outputs that define the address of a byte (or the most significant
byte) to be transferred during a bus cycle. The MC68307 places the address on the bus at
the beginning of a bus cycle, it is valid while the address strobe output (AS) is asserted. The
complete address bus (A23–A0) is capable of addressing 16 Mbytes of data.
The address bus signals are three-stated when the MC68307 is arbitrated off the bus by an
external bus master. They are also three-stated during reset of the EC000 core.
The address bus consists of the following groups of signals. Refer to Section 3 Bus Oper-
ation for information on the address bus and its relationship to bus operation.
2.1.1.1 ADDRESS BUS (A23–A8). These signals are always used as address output lines.
They are valid when address strobe (AS) is asserted. Chip-selected memory and peripher-
als, including 8051-compatible bus devices, need not decode the upper address bits,
depending on the programmed block size for that chip select.
2.1.1.2 ADDRESS BUS (AD7–AD0). In addition to carrying eight address signals A7–A0,
these low-order address lines also carry the 8-bit data bus during 8051-compatible bus
cycles, as indicated by the relevant strobe signals (RD and WR). At the start of each type of
bus cycle (both M68000 and 8051-compatible), they carry the eight low-order address bits
A7–A0. In M68000 bus cycles, they are valid addresses when address strobe (AS) is
asserted. Chip select 3 (CS3) should be used to distinguish 8051 bus cycles if necessary.
Table 2-8. Timer Module Signal Summary
Signal Name
Mnemonic
Input/
Output
Three-State During
Bus Arbitration
Pullup Resistor
Required
Timer Input 1
TIN1/PB6
Input (1)
—
(2)
Timer Input 2
TIN2/PB7
Input (1)
—
(2)
Timer Output 1
TOUT1/PA3
Output (1)
—
Timer Output 2
TOUT2/PA4
Output (1)
—
NOTES:
1. These signals have dual functions as port A and port B I/O lines. Their function is programmed in the port A or port B
control register.
2. Pullup may be required (value depends on individual application). If used as timer inputs, these pins must not be left
oating.
Table 2-9. M-Bus Module Signal Summary
Signal Name
Mnemonic
Input/
Output
Three-State During
Bus Arbitration
Pullup Resistor
Required
M-Bus clock
SCL/PB0
I/O (1)
—
2.2 K
M-Bus data
SDA/PB1
I/O (1)
—
2.2 K
NOTE:
1. These signals have dual functions as port B I/O lines. Their function is programmed in the port B control register.
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