System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-39
set. To avoid altering the IPL field values when only a pending interrupt reset is required,
use an AND.B, AND.W or AND.L operation with an immediate value containing ones for
the PIRx bit positions required to be set, with the corresponding IPL fields set to 111.
1 = The corresponding INT1–INT8 interrupt latch is cleared, so that a pending interrupt
on that line is discarded. The new IPL value for that interrupt source is stored (write
cycle).
0 = The corresponding INT1–INT8 interrupt latch is unaffected. Any pending interrupt
on that line remains pending. The IPL value for that source remains unchanged
(write cycle).
INT1IPL(2–0)–INT8IPL(2–0)—Interrupt Priority Level 1–8
These bits allow the user to specify the IPL for the corresponding general-purpose latched
interrupt input line. When an interrupt occurs, the interrupt controller logic asserts the cor-
rect priority code on the EC000 interrupt level inputs, and respond to the subsequent ac-
knowledge cycle by outputting the correct vector. The IPL for any of the 8 external
interrupt sources INT1–INT8 can only be changed if the corresponding PIRx bit is also
written as 1.
000 =
The corresponding INT1–INT8 interrupt line is inhibited and cannot generate
interrupts. Its state can still be read via the port B registers.
001–111= The corresponding INT1–INT8 interrupt line is enabled, and can generate an
interrupt to the EC000 core processor with the indicated priority level.
NOTE
Do not write a 1 to a PIR bit without also supplying the correct
IPL2–IPL0 value for that interrupt channel. The IPL2–IPL0 value
is written, and if ‘000’ is supplied, then that channel is effectively
disabled. Use the AND method as described above.
5.2.4.2 PERIPHERAL INTERRUPT CONTROL REGISTER (PICR). This register controls
the interrupt priorities for the interrupt signals from the MC68307 internal I/O modules, in the
same way as the latched interrupt control registers do so for the external latched interrupt
input lines The modules which can provide interrupts to the EC000 core processor are: the
M-bus interface module, the timer module (both channels), and the UART interface module.
Each of these sources has four bits assigned to it in the peripheral interrupt control register.
The PICR can be read or written at any time. When read, the data returned is the last value
that was written to the register. This register can be accessed by either word (16-bit) or byte
(8-bit) data transfer instructions. An 8-bit write to one half of the register leaves the other half
intact.
PICR
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
T1IPL(2–0)
—
T2IPL(2–0)
—
UAIPL(2–0)
—
MBIPL(2–0)
RESET:
X
0
X
0
X
0
X
0
Read/Write
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