參數(shù)資料
型號(hào): MC68307PU16V
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 84/264頁(yè)
文件大?。?/td> 949K
代理商: MC68307PU16V
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Serial Module
8-14
MC68307 USER’S MANUAL
MOTOROLA
8.3.5 Bus Operation
This section describes the operation of the bus during read, write, and interrupt acknowl-
edge cycles to the serial module. All serial module registers must be accessed as bytes.
8.3.5.1 READ CYCLES. The serial module is accessed by the CPU with zero wait states,
as the MC68307 system clock is also used for the serial module. The serial module
responds to reads with byte data on D7–D0. Reserved registers return logic zero during
reads.
8.3.5.2 WRITE CYCLES. The serial module is accessed by the CPU with zero wait states.
The serial module accepts write data on D7–D0. Write cycles to read-only registers and
reserved registers complete in a normal manner without exception processing; however, the
data is ignored.
8.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of arbitrat-
ing for interrupt servicing and supplying the interrupt vector when it has successfully won
arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the
interrupt vector register (UIVR) must be initialized. If the UIVR is not initialized, a spurious
interrupt exception is taken if interrupts are generated. This works in conjunction with the
MC68307 interrupt controller, which allows a programmable IPL for the interrupt.
8.4 REGISTER DESCRIPTION AND PROGRAMMING
This section contains a detailed description of each register and its specific function as well
as flowcharts of basic serial module programming.
8.4.1 Register Description
The operation of the serial module is controlled by writing control bytes into the appropriate
registers. A list of serial module registers and their associated addresses is shown in Table
NOTE
All serial module registers are only accessible as bytes. The
contents of the mode registers (UMR1 and UMR2), clock-select
register (UCSR), and the auxiliary control register (UACR) bit 7
should only be changed after the receiver/transmitter is issued a
software RESET command—i.e., channel operation must be
disabled. Care should also be taken if the register contents are
changed during receiver/transmitter operations, as undesirable
results may be produced.
In the registers discussed in the following pages, the numbers above the register description
represent the bit position in the register. The register description contains the mnemonic for
the bit. The values shown below the register description are the values of those register bits
after a hardware reset. A value of U indicates that the bit value is unaffected by reset. The
read/write status is shown in the last line.
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