EC000 Core Processor
MOTOROLA
MC68307 USER’S MANUAL
4-9
4.5 EXCEPTION PROCESSING
This section describes the processing for each type of exception, exception priorities, the
return from an exception, and bus fault recovery. This section also describes the formats of
the exception stack frames.
Exception processing is the activity performed by the processor in preparing to execute a
special routine for any condition that causes an exception. In particular, exception
processing does not include the execution of the routine itself. Exception processing is the
transition from the normal processing of a program to the processing required for any special
internal or external condition that preempts normal processing. External conditions that
cause exceptions are interrupts from external devices, bus errors, and resets. Internal
conditions that cause exceptions are instructions, address errors, and tracing. For example,
the TRAP, TRAPV, CHK, RTE, and DIV instructions can generate exceptions as part of their
normal execution. In addition, illegal instructions and privilege violations cause exceptions.
Exception processing uses an exception vector table and an exception stack frame.
Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not guaranteed
to occur in the order in which they are described in this section.
Figure 4-4 illustrates a gen-
eral flowchart for the steps taken by the processor during exception processing.
During the first step, the processor makes an internal copy of the status register, S-bit, T-
bits, I-bits (SR). Then the processor changes to the supervisor mode by setting the S-bit and
inhibits tracing of the exception handler by clearing the trace enable (T) bit in the SR. For
the reset and interrupt exceptions, the processor also updates the interrupt priority mask in
the SR
During the second step, the processor determines the vector number for the exception. For
interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the vector
number. For all other exceptions, internal logic provides the vector number. This vector num-
ber is used in the last step to calculate the address of the exception vector. Throughout this
section, vector numbers are given in decimal notation.
The third step is to save the current processor contents for all exceptions other than reset
exception, which does not stack information. The processor creates an exception stack
frame on the active supervisor stack and fills it with information appropriate for the type of
TAS
Destination Tested
Condition Codes;
1
bit 7 of Destination
TAS <ea>
TRAP
SSP – 2
SSP; Format ÷ Offset (SSP);
SSP – 4
SSP; PC (SSP); SSP – 2 SSP;
SR
(SSP); Vector Address PC
TRAP #<vector>
TRAPV
If V
then TRAP
TRAPV
TST
Destination Tested
Condition Codes
TST <ea>
UNLK
An
SP; (SP) An; SP + 4 SP
UNLK An
NOTES:
1. d is direction, left or right.
2. List refers to register.
Table 4-4. EC000 Core Instruction Set Summary (Continued)