System Integration Module
5-2
MC68307 USER’S MANUAL
MOTOROLA
5.1 MODULE OPERATION
The various internal functional blocks of the SIM are described here, with a description of
operation of each, along with methods and recommendations for programming the register
locations that configure the MC68307 to suit the user's target system.
5.1.1 MC68307 System Configuration
The MC68307 system configuration logic consists of a module base address register
(MBAR), and a system control register (SCR) which together allow the user to configure op-
eration of the following functions:
Base Address and Address Space of Internal Peripheral Registers
Low-Power (Standby) Modes
Hardware Watchdog Modes for System Protection
8051-Compatible Bus Enable or Disable
Peripheral Chip Selects Enable or Disable
Data Bus Size Control for Chip Selected Address Ranges
5.1.1.1 MODULE BASE ADDRESS REGISTER OPERATION. The
MBAR,
must
be
programmed upon cold reset in order to specify the base address of the various registers
which comprise the SIM and the other on-chip peripherals. The format of this register is
described later in this section, along with a description of the complete memory map of the
EC000 internal registers and peripherals.
The on-chip peripherals require a reserved 4096-byte block of address space for their
registers. This block location is determined by writing the intended base address to the
MBAR in supervisor data space. The MBAR is an on-chip read/write register which is
located at an unused vector entry in the MC68307 vector table. The address of the MBAR
entry within the vector table is $0000F2; it is a 16-bit value. For further details, refer to
The module base address and on-chip peripherals address decode logic block diagram is
After a cold reset, the on-chip peripheral base address is undefined and it is not possible to
access the on-chip peripherals at any address until the MBAR is written. The MBAR and the
SCR can always be accessed at their fixed addresses.
Do not assign other devices on the system bus an address that falls within the address
range of the on-chip peripherals defined by the MBAR. Bus contention could result if this is
done inadvertently. If this happens, the address decode conflict (ADC) status bit in the SCR
is set. This can cause a BERR to be generated, if the address decode conflict enable
(ADCE) bit in the SCR is set.