參數(shù)資料
型號: MC68711E20VFNE2
廠商: Freescale Semiconductor
文件頁數(shù): 136/138頁
文件大小: 0K
描述: IC MCU 8BIT 52-PLCC
標(biāo)準(zhǔn)包裝: 23
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 20KB(20K x 8)
程序存儲器類型: OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 52-LCC(J 形引線)
包裝: 管件
Output Compare (OC)
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
97
PR1 and PR0 — Timer Prescaler Select Bits
These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be
written once only, and the write must be within 64 cycles after reset. Refer to Table 8-4 for specific
timing values.
8.4.10 Timer Interrupt Flag 2 Register
The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system events have occurred.
Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same
position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Always read 0.
Table 8-4. Timer Prescale
PR1 and PR0
Prescaler
0 0
1
0 1
4
1 0
8
1 1
16
Address:
$0025
Bit 7
654321
Bit 0
Read:
TOF
RTIF
PAOVF
PAIF
0000
Write:
Reset:
00000000
Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2)
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