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| 型號(hào)： | MC68711E20VFNE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 63/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 標(biāo)準(zhǔn)包裝： | 23 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲(chǔ)器容量： | 20KB（20K x 8） |
| 程序存儲(chǔ)器類型： | OTP |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 包裝： | 管件 |
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Operating Modes and Memory
MC68HC711D3 Data Sheet, Rev. 2.1
30
Freescale Semiconductor
RAM2–RAM0 (INIT bits 7–4) specify the starting address for the 192 bytes of static RAM. REG3–REG0
(INIT bits 3–0) specify the starting address for the control and status register block. In each case, the four
RAM or REG bits become the four upper bits of the 16-bit address of the RAM or register. Since the INIT
register is set to $00 by reset, the internal registers begin at $0000 and RAM begins at $0040.
Throughout this document, control and status register addresses are displayed with the high-order digit
shown as a bold 0. This convention indicates that the register block may be relocated to any 4-K memory
page, but that its default location is $0000.
RAM and the control and status registers can be relocated independently. If the control and status
registers are relocated in such a way as to conflict with PROM, then the register block takes priority, and
the EPROM or OTPROM at those locations becomes inaccessible. No harmful conflicts result. Lower
priority resources simply become inaccessible. Similarly, if an internal resource conflicts with an external
device, no harmful conflict results, since data from the external device is not applied to the internal data
bus. Thus, it cannot interfere with the internal read.
NOTE
There are unused register locations in the 64-byte control and status
register block. Reads of these unused registers return data from the
undriven internal data bus, not from another source that happens to be
located at the same address.
2.3.3 Configuration Control Register
The configuration control register (CONFIG) controls the presence of OTPROM or EPROM in the memory
map and enables the computer operating properly (COP) watchdog system.
This register is writable only once in expanded and single-chip modes (SMOD = 0). In these mode, the
COP watchdog timer is enabled out of reset. In all modes, except normal expanded, EPROM is enabled
and located at $F000–$FFFF. In normal expanded mode, EPROM is enabled and located at
$7000–$7FFF. Should the user wish to be in expanded mode, but with EPROM mapped at
$F000–$FFFF, he must reset in single-chip mode, and write a 1 to the MDA bit in the HPRIO register.
Bits 7–3 and 0 — Not implemented
Always read 0.
NOCOP — Computer Operating Properly System Disable Bit
This bit is cleared out of reset in normal modes (single chip and expanded), enabling the COP system.
It is writable only once after reset in these modes (SMOD = 0). In the special modes (test and
bootstrap) (SMOD = 1), this bit comes out of reset set, and is writable any time.
1 = COP system is disabled.
0 = COP system is enabled, reset forced on timeout.
Address: $003F
Bit 7
654321
Bit 0
Read:
00000
NOCOP
ROMON
0
Write:
Reset:
00000
U
0
U = Unaffected
Figure 2-4. Configuration Control Register (CONFIG)
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