參數(shù)資料
型號: MC68711E20VFNE2
廠商: Freescale Semiconductor
文件頁數(shù): 21/138頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 52-PLCC
標準包裝: 23
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設備: POR,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 20KB(20K x 8)
程序存儲器類型: OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 8x8b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 52-LCC(J 形引線)
包裝: 管件
Serial Peripheral Interface Timing
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
117
9.9 Serial Peripheral Interface Timing
Num
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
2.0 MHz
3.0 MHz
Unit
Min
Max
Min
Max
Operating frequency
Master
Slave
fop(m)
fop(s)
dc
0.5
2.0
dc
0.5
3.0
fop
MHz
1
Cycle time
Master
Slave
tcyc(m)
tCYC(s)
2.0
500
2.0
333
tcyc
ns
2
Enable lead time
Master(2)
Slave
2. Signal production depends on software.
tlead(m)
tlead(s)
250
240
ns
3
Enable lag time
Master(2)
Slave
tlag(m)
tlag(s)
250
240
ns
4
Clock (SCK) high time
Master
Slave
tw(SCKH)m
tw(SCKH)s
340
190
227
127
ns
5
Clock (SCK) low time
Master
Slave
tw(SCKL)m
tw(SCKL)s
340
190
227
127
ns
6
Data setup time (inputs)
Master
Slave
tsu(m)
tsu(s)
100
100
ns
7
Data hold time (inputs)
Master
Slave
th(m)
th(s)
100
100
ns
8
Access time (time to data active from high-impedance state)
Slave
ta
0
120
0
120
ns
9
Disable time (hold time to high-impedance state)
Slave
tdis
240
167
ns
10
Data valid (after enable edge)(3)
3. Assumes 200 pF load on all SPI pins.
tv(s)
240
167
ns
11
Data hold time (outputs) (after enable edge)
tho
0—
0
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
trm
trs
100
2.0
100
2.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tfm
tfs
100
2.0
100
2.0
ns
s
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