參數(shù)資料
型號： MC68711E20VFNE2
廠商： Freescale Semiconductor
文件頁數(shù)： 137/138頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 52-PLCC
標準包裝： 23
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 38
程序存儲器容量： 20KB（20K x 8）
程序存儲器類型： OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 52-LCC（J 形引線）
包裝： 管件
Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
98
Freescale Semiconductor
8.5 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled
and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII
bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product
of the MCU oscillator frequency and the value of bits RTR1 and RTR0. Refer to Table 8-5 for the periodic
real-time interrupt rates.
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except
by reset. This clock causes the time between successive RTI timeouts to be a constant that is
independent of the software latencies associated with flag clearing and service. For this reason, an RTI
period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire real-time interrupt period elapses before the RTIF flag is set for the first time. Refer
to the TMSK2, TFLG2, and PACTL registers.
8.5.1 Timer Interrupt Mask 2 Register
The timer interrupt mask 2 register (TMSK2) contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable Bit
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits 3–2 — Unimplemented
Always read 0.
Table 8-5. Periodic Real-Time Interrupt Rates
RTR1
and RTR0
E = 1 MHz
E = 2 MHz
E = 3 MHz
E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
Address:
$0024
Bit 7
654321
Bit 0
Read:
TOI
RTII
PAOVI
PAII
0
PR1
PR0
Write:
Reset:
00000000
Figure 8-16. Timer Interrupt Mask 2 Register (TMSK2)
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