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參數(shù)資料
| 型號(hào)： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁(yè)數(shù)： | 41/128頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
41
the longest possible life expectancy. This method requires stopping the program/erase sequence at pe-
riods of t
PPULSE
(t
EPULSE
for erasing) to determine if the Flash EEPROM is programmed/erased. After
the location reaches the proper value, it must continue to be programmed/erased with additional margin
pulses to ensure that it will remain programmed/erased. Failure to provide the margin pulses could lead
to corrupted or unreliable data.
Program/Erase Sequence
— To begin a program or erase sequence the external V
FP
voltage must
be applied and stabilized. The ERAS bit must be set or cleared, depending on whether a program se-
quence or an erase sequence is to occur. The LAT bit will be set to cause any subsequent data written
to a valid address within the Flash EEPROM to be latched into the programming address and data latch-
es. The next Flash array write cycle must be either to the location that is to be programmed if a pro-
gramming sequence is being performed, or, if erasing, to any valid Flash EEPROM array location.
Writing the new address and data information to the Flash EEPROM is followed by assertion of ENPE
to turn on the program/erase voltage to program/erase the new location(s). The LAT bit must be assert-
ed and the address and data latched to allow the setting of the ENPE control bit. If the data and address
have not been latched, an attempt to assert ENPE will be ignored and ENPE will remain negated after
the write cycle to FEECTL is completed. The LAT bit must remain asserted and the ERAS bit must re-
main in its current state as long as ENPE is asserted. A write to the LAT bit to clear it while ENPE is set
will be ignored. That is, after the write cycle, LAT will remain asserted. Likewise, an attempt to change
the state of ERAS will be ignored and the state of the ERAS bit will remain unchanged.
The programming software is responsible for all timing during a program sequence. This includes the
total number of program pulses (n
PP
), the length of the program pulse (t
PPULSE
), the program margin
pulses (p
m
) and the delay between turning off the high voltage and verifying the operation (t
VPROG
).
The erase software is responsible for all timing during an erase sequence. This includes the total num-
ber of erase pulses (e
m
), the length of the erase pulse (t
), the erase margin pulse or pulses, and
the delay between turning off the high voltage and verifying the operation (t
VERASE
).
Software also controls the supply of the proper program/erase voltage to the V
FP
pin, and should be at
the proper level before ENPE is set during a program/erase sequence.
A program/erase cycle should not be in progress when starting another program/erase, or while at-
tempting to read from the array.
NOTE
Although clearing ENPE disables the program/erase voltage (V
FP
) from the V
FP
pin to the array, care must be taken to ensure that V
FP
is at V
DD
whenever pro-
gramming/erasing is not in progress. Not doing so could damage the part. Ensuring
that V
FP
is always greater or equal to V
DD
can be accomplished by controlling the
V
FP
power supply with the programming software via an output pin. Alternatively,
all programming and erasing can be done prior to installing the device on an appli-
cation circuit board which can always connect V
FP
to V
DD
. Programming can also
be accomplished by plugging the board into a special programming fixture which
provides program/erase voltage to the V
FP
pin.
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