參數(shù)資料
型號： MC68B912B32
廠商： Motorola, Inc.
英文描述： 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述： 16位微控制器
文件頁數(shù)： 99/128頁
文件大?。?/td> 748K
代理商： MC68B912B32
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
99
14.3 Loopback Modes
Two loopback modes are used to determine the source of bus faults.
Digital Loopback
is used to determine if a bus fault has been caused by failure in the node’s internal
circuits or elsewhere in the network, including the node’s analog physical interface. In this mode, the
receive digital input (RxPD) is disconnected from the analog transceiver’s receive output. RxPD is then
connected internally to the transmit digital output (TxPD) to form the loopback connection. The analog
transceiver’s transmit input is still driven by TxPD in this mode.
Analog Loopback
is used to determine if a bus fault has been caused by a failure in the node's off-chip
analog transceiver or elsewhere in the network. The BDLC analog loopback mode does not modify the
digital transmit or receive functions of the BDLC. It does, however, ensure that once analog loopback
mode is exited, the BDLC will wait for an idle bus condition before participation in network communica-
tion resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the input to the
output drive stage to be looped back into the receiver, allowing the node to receive messages it has
transmitted without driving the J1850 bus. In this mode, the output to the J1850 bus is typically high
impedance. This allows the communication path through the analog transceiver to be tested without in-
terfering with network activity. Using the BDLC analog loopback mode in conjunction with the analog
transceiver's loopback mode ensures that, once the off-chip analog transceiver has exited loopback
mode, the BDLC will not begin communicating before a known condition exists on the J1850 bus.
14.4 BDLC Registers
Eight registers are available for controlling operation of the BDLC and for communicating data and sta-
tus information. A full description of each register follows.
IMSG — Ignore Message
Disables the receiver until a new start-of-frame (SOF) is detected.
0 = Enable Receiver
1 = Disable Receiver
CLKS — Clock Select
Designates nominal BDLC operating frequency (f
bdlc
) for J1850 bus communication and automatic ad-
justment of symbol time.
0 = Integer frequency (1 MHz)
1 = Binary frequency (1.048576 MHz)
R1, R0 — Rate Select
Determines the divisor of the MCU system clock frequency (f
TCLKS
) to form the BLDC operating fre-
quency (f
BDLC
). These bits may be written only once after reset.
The selected value depends upon the MCU system clock frequency according to
Table 32
or
Table 33
.
BCR1 —
BDLC Control Register 1
$00F8
Bit 7
6
5
4
3
2
1
Bit 0
IMSG
CLCKS
R1
R0
0
0
IE
WCM
RESET:
1
1
1
0
0
0
0
0
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