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參數(shù)資料
| 型號(hào)： | MC68B912B32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| 中文描述： | 16位微控制器 |
| 文件頁(yè)數(shù)： | 55/128頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | MC68B912B32 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
55
9.5.2 Clock and Watchdog Control Logic
The COP watchdog system is enabled, with the CR[2:0] bits set for the shortest duration time-out. The
clock monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The
rate control bits are cleared, and must be initialized before the RTI system is used. The DLY control bit
is set to specify an oscillator start-up delay upon recovery from STOP mode.
9.5.3 Interrupts
PSEL is initialized in the HPRIO register with the value $F2, causing the external IRQ pin to have the
highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR sys-
tems). However, the interrupt mask bits in the CPU12 CCR are set to mask X and I related interrupt
requests.
9.5.4 Parallel I/O
If the MCU comes out of reset in an expanded mode, port A and port B are used for the multiplexed
address/data bus and port E pins are normally used to control the external bus (operation of port E pins
can be affected by the PEAR register). If the MCU comes out of reset in a single-chip mode, all ports
are configured as general-purpose high-impedance inputs. Port S, port T, port DLC, port P, and port AD
are all configured as general-purpose inputs.
9.5.5 Central Processing Unit
After reset, the CPU fetches a vector from the appropriate address, then begins executing instructions.
The stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and
I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
9.5.6 Memory
After reset, the internal register block is located at $0000–$01FF, the register-following space is at
$0200–$03FF, and RAM is at $0800–$0BFF. EEPROM is located at $0D00–$0FFF. Flash EEPROM
is located at $8000–$FFFF in single-chip modes and at $0000–$7FFF (but disabled) in expanded
modes.
9.5.7 Other Resources
The timer, serial communications interface (SCI), serial peripheral interface (SPI), byte data link con-
troller (BDLC), pulse-width modulator (PWM), and analog-to-digital converter (ATD) are off after reset.
9.6 Register Stacking
Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared.
When an interrupt service request is recognized, the CPU responds at the completion of the instruction
being executed. Interrupt latency varies according to the number of cycles required to complete the in-
struction. Some of the longer instructions can be interrupted and will resume normally after servicing
the interrupt.
When the CPU begins to service an interrupt, the instruction queue is cleared, the return address is cal-
culated, and then it and the contents of the CPU registers are stacked as shown in
Table 18
.
Table 18 Stacking Order on Entry to Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
CPU Registers
RTN
H
: RTN
L
Y
H
: Y
L
X
H
: X
L
B : A
CCR
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