參數(shù)資料
型號(hào)： MC68B912B32
廠商： Motorola, Inc.
英文描述： 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述： 16位微控制器
文件頁(yè)數(shù)： 77/128頁(yè)
文件大小： 748K
代理商： MC68B912B32
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
77
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the cor-
responding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled
to cause a hardware interrupt.
Read or write anytime.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.
Read or write anytime.
TOI — Timer Overflow Interrupt Enable
0 = Interrupt inhibited
1 = Hardware interrupt requested when TOF flag set
PUPT — Timer Pull-Up Resistor Enable
This enable bit controls pull-up resistors on the timer port pins when the pins are configured as inputs.
1 = Enable pull-up resistor function
0 = Disable pull-up resistor function
RDPT — Timer Drive Reduction
This bit reduces the effective output driver size which can reduce power supply current and generated
noise depending upon pin loading.
1 = Enable output drive reduction function
0 = Normal output drive capability
TCRE — Timer Counter Reset Enable
This bit allows the timer counter to be reset by a successful output compare 7 event.
0 = Counter reset inhibited and counter free runs
1 = Counter reset by a successful output compare 7
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1,
TOF will never get set even though TCNT will count from $0000 through $FFFF.
PR2, PR1, PR0 — Timer Prescaler Select
These three bits specify the number of
÷
2 stages that are to be inserted between the module clock and
the timer counter.
TMSK1
— Timer Interrupt Mask 1
$008C
Bit 7
6
5
4
3
2
1
Bit 0
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
RESET:
0
0
0
0
0
0
0
0
TMSK2
— Timer Interrupt Mask 2
$008D
Bit 7
6
5
4
3
2
1
Bit 0
TOI
0
PUPT
RDPT
TCRE
PR2
PR1
PR0
RESET:
0
0
0
0
0
0
0
0
Table 26 Prescaler Selection
PR2
PR1
PR0
Prescale
Factor
1
2
4
8
16
32
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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