參數(shù)資料
型號: MC68B912B32
廠商: Motorola, Inc.
英文描述: 2.5V 100ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125
中文描述: 16位微控制器
文件頁數(shù): 66/128頁
文件大小: 748K
代理商: MC68B912B32
MOTOROLA
66
MC68HC912B32
MC68HC912B32TS/D
CON01 — Concatenate PWM Channels 0 and 1
When concatenated, channel 0 becomes the high-order byte and channel 1 becomes the low-order
byte. Channel 0 output pin is used as the output for this 16-bit PWM (bit 0 of port P). Channel 1 clock-
select control bits determine the clock source.
0 = Channels 0 and 1 are separate 8-bit PWMs.
1 = Channels 0 and 1 are concatenated to create one 16-bit PWM channel.
PCKA2 – PCKA0 — Prescaler for Clock A
Clock A is one of two clock sources which may be used for channels 0 and 1. These three bits determine
the rate of clock A, as shown in
Table 22
.
PCKB2 – PCKB0 — Prescaler for Clock B
Clock B is one of two clock sources which may be used for channels 2 and 3. These three bits determine
the rate of clock B, as shown in
Table 22
.
Read and write anytime.
PCLK3 — PWM Channel 3 Clock Select
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
PCLK2 — PWM Channel 2 Clock Select
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
PCLK1 — PWM Channel 1 Clock Select
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
PCLK0 — PWM Channel 0 Clock Select
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may
occur during the transition.
Table 22 Clock A and Clock B Prescaler
PCKA2
(PCKB2)
0
0
0
0
1
1
1
1
PCKA1
(PCKB1)
0
0
1
1
0
0
1
1
PCKA0
(PCKB0)
0
1
0
1
0
1
0
1
Value of
Clock A (B)
P
P
÷
2
P
÷
4
P
÷
8
P
÷
16
P
÷
32
P
÷
64
P
÷
128
PWPOL —
PWM Clock Select and Polarity
$0041
Bit 7
6
5
4
3
2
1
Bit 0
PCLK3
PCLK2
PCLK1
PCLK0
PPOL3
PPOL2
PPOL1
PPOL0
RESET:
0
0
0
0
0
0
0
0
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