Serial Communication Controllers (SCCs)
7-260
MC68360 USER’S MANUAL
MOTOROLA
NOTE: Entries in boldface must be initialized by the user.
E—Empty
0 = The data buffer associated with this Rx BD has been filled with received data, or
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
1 = The data buffer associated with this Rx BD is empty, or reception is currently in
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E bit is set, the CPU32+ core should not write any fields of this Rx BD.
Bits 14, 9–6—Reserved
W—Wrap (Final BD in Table)
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BD s in this table is programmable and is determined only by
the W-bit and the overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer has been used.
1 = The RXB bit or RXF bit in the Ethernet event register will be set when this buffer
has been used by the Ethernet controller. These two bits may cause interrupts if
they are enabled.
L—Last in Frame
This bit is set by the Ethernet controller when this buffer is the last in a frame. This implies
the end of the frame or reception of an error, in which case one or more of the CL, OV,
CR, SH, NO, and LG bits are set. The Ethernet controller will write the number of frame
octets to the data length field.
0 = The buffer is not the last in a frame.
1 = The buffer is the last in a frame.
F—First in Frame
This bit is set by the Ethernet controller when this buffer is the first in a frame.
0 = The buffer is not the first in a frame.
1 = The buffer is the first in a frame.
M—Miss
This bit is set by the Ethernet controller for frames that were accepted in promiscuous
mode, but were flagged as a "miss" by the internal address recognition. Thus, while in pro-
15
E
14
—
13
W
12
I
11
L
10
F
9
—
8
—
7
—
6
—
5
4
3
2
1
0
OFFSET + 0
OFFSET + 2
LG
NO
SH
CR
OV
CL
DATA LENGTH
OFFSET + 4
RX DATA BUFFER POINTER
OFFSET + 6