CPM Interrupt Controller (CPIC)
7-380
MC68360 USER’S MANUAL
MOTOROLA
7.15.5.3 CPM INTERRUPT MASK REGISTER (CIMR).
Each bit in the 32-bit read-write
CIMR corresponds to a CPM interrupt source. The user masks an interrupt by clearing the
corresponding bit in the CIMR and enables an interrupt by setting the corresponding bit in
the CIMR. When a masked CPM interrupt occurs, the corresponding bit in the CIPR is still
set, regardless of the CIMR bit, but no interrupt request is passed to the CPU32+ core.
If a CPM interrupt source is requesting interrupt service when the user clears its CIMR bit,
the request will cease. If its CIMR bit is later set by the user, a previously pending interrupt
request will be processed by the CPU32+ core, according to its assigned priority. The CIMR
can be read by the user at any time. The CIMR is cleared at reset.
NOTES
The SCC CIMR bit positions are NOT affected by the relative pri-
ority between SCCs (as determined by the SCxP and SPS bits
in the CICR).
To clear bits that were set by multiple interrupt events, the user
must clear all the unmasked events in the corresponding event
register.
If a bit in the CIMR is masked at the same time that the corre-
sponding CIPR bit causes an interrupt request to the IMB, then
the interrupt is not processed, but the error vector is issued if the
interrupt acknowledge cycle occurs with no other CPM interrupts
pending. Thus, the user should always include an error vector
routine, even if it just contains the RTE instruction.
The error vector cannot be masked.
7.15.5.4 CPM INTERRUPT IN-SERVICE REGISTER (CISR).
Each bit in the 32-bit read-
write CISR corresponds to a CPM interrupt source. In a vectored interrupt environment, the
CPIC sets the CISR bit when the vector number corresponding to the CPM interrupt source
is passed during an interrupt acknowledge cycle. The user’s interrupt service routine must
clear this bit after servicing is complete. (If an event register exists for this peripheral, its bits
would normally be cleared as well.) To clear a bit in the CISR, the user writes a one to that
bit. Since the user can only clear bits in this register, bits written as zeros will not be affected.
The CISR is cleared at reset.
31
PC0
15
30
29
28
27
26
PC1
10
25
24
PC2
8
23
PC3
7
22
21
20
19
—
3
18
171
R–TT
1
16
—
0
SCC1
14
SCC2
13
SCC3
12
SCC4
11
TIMER1
9
SDMA
6
IDMA1
5
IDMA2
4
TIMER2
2
PC4
PC5
—
TIMER3
PC6
PC7
PC8
—
TIMER4
PC9
SPI
SMC1
SMC2 /
PIP
PC10
PC11
—
31
PC0
15
30
29
28
27
26
PC1
10
25
24
PC2
8
23
PC3
7
22
21
20
19
—
3
18
171
R–TT
1
16
—
0
SCC1
14
SCC2
13
SCC3
12
SCC4
11
TIMER1
9
SDMA
6
IDMA1
5
IDMA2
4
TIMER2
2
PC4
PC5
—
TIMER3
PC6
PC7
PC8
—
TIMER4
PC9
SPI
SMC1
SMC2 /
PIP
PC10
PC11
—