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參數(shù)資料
| 型號： | MC68HC05J3CP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 43/92頁 |
| 文件大?。?/td> | 912K |
| 代理商： | MC68HC05J3CP |
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MOTOROLA
6-8
MC68HC05J3
16-BIT PROGRAMMABLE TIMER
6
(locations) if the MSB is written rst. A write made only to the LSB will not inhibit the compare
function. The processor can write to either byte of the output compare register without affecting
the other byte. The output level (OLV) bit is clocked to the output level register whether the output
compare ag (OCF) is set or clear. The minimum time required to update the output compare
register is a function of the program rather than the internal hardware. Because the output
compare ag and the output compare register are not dened at power on, and not affected by
reset, care must be taken when initialising output compare functions with software. The following
procedure is recommended:
1) write to output compare high to inhibit further compares;
2) read the timer status register to clear OCF (if set);
3) write to output compare low to enable the output compare function.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.3
Timer during WAIT mode
In WAIT mode all CPU action is suspended, but the programmable timer continues counting. An
interrupt from an input capture, an output compare or a timer overow, if enabled, will cause the
processor to exit WAIT mode.
6.4
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, hence the timer stops counting. If STOP is exited
by an interrupt the counter retains the last count value. If the device is reset, then the counter is
forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pin, the
input capture detect circuit is armed. This does not set any timer ags nor wake up the MCU. When
the MCU does wake up, however, there is an active input capture ag and data from the rst valid
edge that occurred during the STOP period. If the device is reset to exit STOP mode, then no input
capture ag or data remains, even if a valid input capture edge occurred.
6.5
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
ag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J3DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit |
| MC68HC05J3P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit |
| MC68HC05J5A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05J5ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
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