參數(shù)資料
型號: MC68HC05J3CP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 48/92頁
文件大?。?/td> 912K
代理商: MC68HC05J3CP
MOTOROLA
7-2
MC68HC05J3
RESETS AND INTERRUPTS
7
7.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specied minimum operating voltage. This may be accomplished by connecting an external
RC-circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be
great enough (at least 100ms) to allow the oscillator circuit to stabilize.
7.1.2
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to
the RESET input for a minimum period of 1.5 machine cycles (tCYC). This pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. When the RESET pin goes high, the
MCU will resume operation on the following cycle.
7.1.3
Computer operating properly (COP) reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specic time by a program reset sequence.
Note:
COP timeout is prevented by periodically writing a ‘0’ to bit 0 of address $0FF0.
If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP timeout was generated.
The COP reset function is enabled or disabled by a mask option (see Section 1.2).
TPG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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