參數(shù)資料
型號: MC68HC05J3CP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 65/92頁
文件大?。?/td> 912K
代理商: MC68HC05J3CP
MOTOROLA
8-10
MC68HC05J3
CPU CORE AND INSTRUCTION SET
8
Table 8-9 M68HC05 opcode map
Bit
manipulation
Branc
h
Read/modify/write
Contr
ol
Register/memor
y
BTB
BSC
REL
DIR
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
High
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
High
Lo
w
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Lo
w
0
0000
5
3
5
3
6
5
9
2
3
4
5
4
3
0
0000
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
R
TI
SUB
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
1
0001
5
3
6
2
3
4
5
4
3
1
0001
BRCLR0
BCLR0
BRN
R
TS
CMP
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
2
0010
5
3
11
2
3
4
5
4
3
2
0010
BRSET1
BSET1
BHI
MUL
SBC
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
3
0011
5
3
5
3
6
5
10
2
3
4
5
4
3
0011
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
SWI
CPX
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
4
0100
5
3
5
3
6
5
2
3
4
5
4
3
4
0100
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
5
0101
5
3
2
3
4
5
4
3
5
0101
BRCLR2
BCLR2
BCS
BIT
3
BTB
2
BSC
2
REL
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
6
0110
5
3
5
3
6
5
2
3
4
5
4
3
6
0110
BRSET3
BSET3
BNE
R
OR
R
ORA
R
ORX
R
OR
R
OR
LD
A
LD
A
LD
A
LD
A
LD
A
LD
A
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
7
0111
5
3
5
3
6
5
2
4
5
6
5
4
7
0111
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
ST
A
ST
A
ST
A
ST
A
ST
A
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
8
1000
5
3
5
3
6
5
2
3
4
5
4
3
8
1000
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
CLC
EOR
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
9
1001
5
3
5
3
6
5
2
3
4
5
4
3
9
1001
BRCLR4
BCLR4
BHCS
R
OL
R
OLA
R
OLX
R
OL
R
OL
SEC
ADC
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
A
1010
5
3
5
3
6
5
2
3
4
5
4
3
A
1010
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
B
1011
5
3
2
3
4
5
4
3
B
1011
BRCLR5
BCLR5
BMI
SEI
ADD
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
C
1100
5
3
5
3
6
5
2
3
4
3
2
C
1100
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
RSP
JMP
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
D
1101
5
3
4
3
5
4
2
6
5
6
7
6
5
D
1101
BRCLR6
BCLR6
BMS
TST
A
TSTX
TST
NOP
BSR
JSR
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
2
REL
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
E
1110
5
3
2
3
4
5
4
3
E
1110
BRSET7
BSET7
BIL
ST
OP
LDX
3
BTB
2
BSC
2
REL
1
INH
2
IMM
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
F
1111
5
3
5
3
6
5
2
4
5
6
5
4
F
1111
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
W
AIT
TXA
STX
3
BTB
2
BSC
2
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
INH
1
INH
2
DIR
3
EXT
3
IX2
2
IX1
1
IX
F
1111
3
0
0000
SUB
1
IX
Opcode
in
he
xadecimal
Opcode
in
binar
y
Address
mode
Cycles
Bytes
Mnemonic
Leg
end
Abbre
viations
f
or
ad
dress
modes
and
register
s
BSC
BTB
DIR
EXT
INH
IMM
IX
IX1
IX2
REL
A
X
Bit
set/clear
Bit
test
and
br
anch
Direct
Extended
Inherent
Immediate
Inde
xed
(no
offset)
Inde
xed,
1
b
yte
(8-
bit)
offset
Inde
xed,
2
b
yte
(16-
bit)
offset
Relativ
e
Accum
ulator
Inde
xregister
Not
implemented
TPG
65
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
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