參數(shù)資料
型號: MC68HC05J5AJDWR3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 32/106頁
文件大?。?/td> 1069K
代理商: MC68HC05J5AJDWR3
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INTERRUPTS
MOTOROLA
REV 2.1
4-5
4.5.1 IRQ CONTROL/STATUS REGISTER (ICSR) $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF, IRQF1, IRQE1 bits are cleared
and IRQE bit is set by reset.
Figure 4-3. IRQ Status & Control Register
IRQR 1 - PA7 Interrupt Acknowledge
The IRQR1 acknowledge bit clears an IRQ interrupt triggered by a falling edge
on PA7 by clearing the IRQ1 latch. The IRQR1 acknowledge bit will always read
as a logic zero.
1 =
Writing a logic one to the IRQR1 acknowledge bit will clear the IRQ1
latch.
0 =
Writing a logic zero to the IRQR1 acknowledge bit will have no effect
on the IRQ1 latch.
IRQR - IRQ Interrupt Acknowledge
The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.
The IRQR acknowledge bit will always read as a logic zero.
1 =
Writing a logic one to the IRQR acknowledge bit will clear the IRQ
latch.
0 =
Writing a logic zero to the IRQR acknowledge bit will have no effect
on the IRQ latch.
IRQF1 - PA7 Interrupt Request Flag
Writing to the IRQF1 ag bit will have no effect on it. If the additional setting of
IRQF1 ag bit is not cleared in the IRQ service routine and the IRQE1 enable
bit remains set the CPU will re-enter the IRQ interrupt sequence continuously
until either the IRQF1 ag bit or the IRQE1 enable bit is cleared. The IRQF1
latch is cleared by reset.
1 =
Indicates that an IRQ request triggered by a falling edge on PA7 is
pending.
0 =
Indicates that no IRQ request triggered by a falling edge on PA7 is
pending. The IRQF1 ag bit can ONLY be cleared by writing a logic
one to the IRQR1 acknowledge bit. Doing so before exiting the
service routine will mask out additional occurrences of the IRQF1.
0
IRQR1
ICSR
$000A
1
7
W
R
0000000
reset
6543210
IRQE
IRQF
0
IRQR
0
IRQF1
IRQE1
0
RESERVED FOR TEST
R
UNIMPLEMENTED
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