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參數(shù)資料
| 型號： | MC68HC05J5AJDWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 34/106頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MC68HC05J5AJDWR3 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INTERRUPTS
MOTOROLA
REV 2.1
4-7
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the output of the logic OR function with the PA0 thru PA3 pins. The state of
the individual Port A pins can be checked by reading the appropriate Port A pins
as inputs.
NOTE
If enabled, the PA0 thru PA3 and PA7 pins will cause an IRQ interrupt regardless
of whether these pins are congured as inputs or outputs.
4.5.3 TIMER INTERRUPT (MFT)
The TIMER interrupt is generated by the multi-function timer when either a timer
overow or a real time interrupt has occurred as described in Section 8. The inter-
rupt ags and enable bits for the Timer interrupts are located in the Timer Control
& Status Register (TCSR) located at $0008. The I-bit in the CCR must be clear in
order for the TIMER interrupt to be enabled. Either of these two interrupts will vec-
tor to the same interrupt service routine located at the address specied by the
contents of memory locations $0FF8 and $0FF9.
4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)
The Timer1 interrupt is generated by the 16-bit Timer when either a timer1 over-
ow or a input capture has occurred as described in Section 9. The interrupt flags
and enable bits for the Timer1 interrupt are located in the Timer1 Control & Status
Register (T1CR & T1SR) located at $0012, $0013. The I-bit in the CCR must be
cleared in order to enable the Timer1. Either of these two interrupts will vector to
the same interrupt service routine located at the address specified by the contents
of memory locations $0FF6 and $0FF7.
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