- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45220 > MC68HC05J5AJDWR3 (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05J5AJDWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 75/106頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MC68HC05J5AJDWR3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當前第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
INSTRUCTION SET
MC68HC05J5A
10-2
REV 2.1
10.1.3 Direct
Direct instructions can access any of the rst 256 memory addresses with two
bytes. The rst byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
10.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
rst byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
10.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the rst 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
10.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the rst 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the rst 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68HC05J5ADWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J5AJDWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| MC68HC05J5CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J5P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05J5DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05J5AJP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05J5AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05JJ6 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification Microcontrollers |
| MC68HC05JJ6CDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification Microcontrollers |
| MC68HC05JJ6CDWE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。