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| 型號： | MC68HC05J5AJDWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 54/106頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MC68HC05J5AJDWR3 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INPUT/OUTPUT PORTS
MOTOROLA
REV 2.1
7-7
If the corresponding bit in the pulldown/up register is clear (and the pulldown/up
mask option is chosen) the input pin will also have an activated pulldown/up
device. Since the pulldown/up register bits are write-only, bit manipulation should
not be used on these register bits.
7.4.4 I/O Pin Transitions
A "glitch" can be generated on an I/O pin when changing it from an input to an out-
put unless the data register is rst preconditioned to the desired state before
changing the corresponding DDR bit from a zero to a one.
If pulldowns are enabled by mask option, a oating input can be avoided by clear-
ing the pulldown/up register bit before changing the corresponding DDR from a
one to a zero. This will insure that the pulldown device will be activated before the
I/O pin changes from a driven output to a pulled low/high input.
7.4.5 I/O Pin Truth Tables
Every pin on Port A and Port B may be programmed as an input or an output
also have software programmable pulldown/up devices if selected by the appropri-
ate mask option.
Table 7-1. Port A I/O Pin Functions
Table 7-2. Port B I/O Pin Functions
Accesses to
PDURA
at $0010
Accesses to
Data Register
@ $0000
0
1
IN, Hi-Z
OUT
PDURA0-7
DDRA0-7
I/O Pin
PA0-7
*
PA0-7
U
I/O Pin Mode
DDRA
Read/Write
Accesses
to DDRA
@ $0004
Read
Write
Read
Write
* Does not affect input,
but stored to data register
U is undefined
Accesses to
PDURB
at $0011
Accesses to
Data Register
@ $0001
0
1
IN, Hi-Z
OUT
PDURB0-2
DDRB0-2
I/O Pin
PB0-5
*
PB0-5
U
I/O Pin Mode
DDRA
Read/Write
Accesses
to DDRB
@ $0005
Read
Write
Read
Write
* Does not affect input,
but stored to data register
U is undefined
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