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參數(shù)資料
| 型號(hào)： | MC68HC05J5AJDWR3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 49/106頁 |
| 文件大小： | 1069K |
| 代理商： | MC68HC05J5AJDWR3 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INPUT/OUTPUT PORTS
MOTOROLA
REV 2.1
7-3
7.2.3 Port A Pulldown/up Register
All Port A I/O pins may have software programmable pulldown/up devices enabled
by the applicable mask option. If the pulldown/up mask option is selected, the pull-
down/up is activated whenever the corresponding bit in the PDURA is clear. If the
corresponding bit in the PDURA bit is set or the mask option for pulldown/up is not
chosen, the pulldown/up will be disabled. A pulldown on an I/O pin is activated
only if the I/O pin is programmed as an input whereas a pullup device on an I/O
pin is always activated whenever enabled, regardless of port direction.
The PDURA is a write-only register. Any reads of location $0010 will return unde-
ned results. Since reset clears both the DDRA and the PDURA, all pins will ini-
tialize as inputs with the pulldown active and pullup devices active (if enabled by
mask option).
Typical value of port A pullup is 5K
.
7.2.4 Port A Drive Capability
The outputs for the upper four bits of Port A (PA4, PA5, PA6 and PA7) are capable
of sinking approximately 8mA of current to VSS.
7.2.5 Port A I/O Pin Interrupts
The inputs to PA0, PA1, PA2, PA3 may be connected to the IRQ input of the CPU
if enabled by a mask option. The input to PA7 is also connected to the IRQ input of
the CPU, yet it is only enabled or disabled by software, not by mask option. PA7
interrupt capability is controlled by a set of control and status bits (IRQE1, IRQF1,
IRQR1), different from the set of control and status bits for that of PA0-PA3 and
IRQ pin (IRQE, IRQF, IRQR) in the same ICSR (Interrupt Control and Status Reg-
ister).
When connected as an alternate source of an IRQ interrupt, PA0-3 input pins will
behave the same as the IRQ pin itself, except that their active state is a logical one
or a rising edge. The IRQ pin has an active state that is a logical zero or a falling
edge. PA7 interrupt occurs, if enabled, only upon the falling edge at the input.
If mask options for both level and edge sensitivity interrupts are chosen, the pres-
ence of a logic one or occurrence of a rising edge on any one of the lower four
Port A pins will cause an IRQ interrupt request. If the edge-only sensitivity is
selected, the occurrence of a rising edge on any one of the lower four Port A pins
will cause an IRQ interrupt request. As long as any one of the lower four Port A
IRQ inputs remains at a logic one level, the other of the lower four Port A IRQ
inputs are effectively ignored.
NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the internal IRQ input to the CPU. Therefore BIH and BIL cannot be used to
test the state of the lower four Port A input pins as a group nor that of PA7.
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