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| 型號： | MC68HC05JB3DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 103/148頁 |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3DW |
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GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
16-BIT TIMER
MC68HC05JB3
9-2
REV 1
The basis of the 16-bit Timer is a 16-bit free-running counter which increases in
count with each internal bus clock cycle. The counter is the timing reference for
the input capture and output compare functions. The input capture and output
compare functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms and timing
delays. Software can read the value in the 16-bit free-running counter at any time
without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a spe-
cic timer function allows full control of that function; however, an access of the
high byte inhibits that specic timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a xed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt ags can be read from the timer status register (TSR) located at
$0013.
9.1
TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 9-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
Figure 9-2. Programmable Timer Counter Block Diagram
T
OIE
TMRH ($0018)
TMR LSB
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
OVERFLOW (TOF)
RESET
CLOCK
INTERRUPT
TMRL ($0019)
TO
F
TIMER STATUS REG.
$0012
$0013
INTERNAL
($FFFC)
DATA
READ
TMRH
READ
TMRL
READ
LATCH
BUS
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