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參數(shù)資料
| 型號(hào)： | MC68HC05JB3DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 89/148頁(yè) |
| 文件大?。?/td> | 1600K |
| 代理商： | MC68HC05JB3DW |
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November 5, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05JB3
LOW POWER MODES
MOTOROLA
REV 1
6-3
6.1
STOP MODE
STOP mode is entered by executing the STOP instruction. This is the lowest
power consumption mode of the MCU. In the STOP Mode the internal oscillator is
turned off, halting all internal processing.
Execution of the STOP instruction automatically clears the I-bit in the Condition
Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so
that the IRQ external interrupt is enabled. All other registers, including the other
bits in the TCSR, and memory remain unaltered. All input/output lines remain
unchanged.
The MCU can be brought out of the STOP Mode by an IRQ external interrupt or a
USB coming out from Suspend Mode Interrupt (Bus activity detection) or an exter-
nally generated RESET, USB Reset or an LVR reset. When exiting the STOP
Mode the internal oscillator will resume after a 224 or 4064 internal processor
clock cycle oscillator stabilization delay.
6.2
WAIT MODE
WAIT mode is entered by executing the WAIT instruction. This places the MCU in
a low-power mode, which consumes more power than the STOP Mode. In the
WAIT Mode the internal processor clock is halted, suspending all processor and
internal bus activity. Execution of the WAIT instruction automatically clears the I-bit
in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/
Status Register so that the IRQ external interrupt is enabled. All other registers,
memory, and input/output lines remain in their previous states.
The WAIT Mode may be exited when an external IRQ, USB, Timer1 or MFT inter-
rupt, an LVR reset, USB reset or an external RESET occurs.
6.3
DATA-RETENTION MODE
The Data-Retention mode is only available if the Low Voltage Reset function
(mask option) is not enabled.
In the data retention mode, the MCU retains RAM contents and CPU register con-
tents at VDD voltages as low as 2Vdc. The data retention feature allows the MCU
to remain in a low power consumption state during which it retains data, but the
CPU cannot execute instructions. The RESET pin must be held low during data-
retention mode.
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