參數(shù)資料
型號: MC68HC05JB3DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 108/148頁
文件大小: 1600K
代理商: MC68HC05JB3DW
GENERAL RELEASE SPECIFICATION
November 5, 1998
MOTOROLA
16-BIT TIMER
MC68HC05JB3
9-6
REV 1
TCMPE — Timer Input Capture Comparator Enable
1 =
Timer input capture comparator is selected.
0 =
Timer input capture comparator schmitt trigger is selected.
NOTE
When the comparator and VDD/2 reference are enabled, PB0 pin will automatically
becomes an input pin, irrespective of DDR setting. However, it is recommended to
set PB0 as an input rst (via DDR), before enabling the comparator. A read of PB0
will reect the TCAP pin status, not the PB0 register bit.
The comparator uses the VDD/2 reference as the compare voltage, resulting in a
typical output as shown in Figure 9-8.
Switching off the VDD/2 voltage reference by clearing TCMPE=0 will further save
power when the MCU is in a low power mode.
Figure 9-7. TCAP Input Signal Conditioning
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OIER
R
TCMPE
VREF2
VREF1
VREF0
OIE3
OIE2
OIE1
OIE0
$000E
W
reset:
00000000
+
MUX
PB0/
TCAP
Voltage
Reference
VREF
EN
PB0 I/O
PORT LOGIC
TCMPE bit
VDD ÷ 2
Schmitt Trigger
Comparator
To edge select and
detect logic
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