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參數(shù)資料
| 型號： | MC68HC05JB4DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 107/134頁 |
| 文件大?。?/td> | 2440K |
| 代理商： | MC68HC05JB4DW |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
UNIVERSAL SERIAL BUS MODULE
REV
Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width is
measured with the same capacitive load used for maximum rise and fall times and
is measured at the same level as the differential signal crossover points of the
data lines.
Figure 10-9. EOP Width Timing
10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USB
data pins of a device. The reset signaling is specied to be present for a minimum
of 10 ms. An active device (powered and not in the suspend state) seeing a
single-ended zero on its USB data inputs for more than 2.5
s may treat that signal
as a reset, but must have interpreted the signaling as a reset within 5.5
s. For a
Low speed device, an SE0 condition between 4 and 8 low speed bit times
represents a valid USB reset.
A USB sourced reset will hold the MC68HC05JB4 in reset for the duration of the
reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be
set after the internal reset is removed (See Section 10.5.2 for more detail).
After a reset is removed, the device will be in the attached, but not yet addressed
or congured state (refer to Section 9.1 of the USB specication). The device must
be able to accept a device address via a SET_ADDRESS command (refer to
section 9.4 of the USB specication) no later than 10 ms after the reset is
removed.
BUS DRIVEN TO
LAST BIT OF
BUS IDLE
EOP
STROBE
PACKET
IDLE STATE
BUS FLOATS
VOH (min)
VSE (max)
VSE (min)
VOL (min)
VSS
EOP
WIDTH
tPeriod
DIFFERENTIAL
DATA LINES
DATA
CROSSOVER
LEVEL
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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