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| 型號(hào)： | MC68HC05JB4DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 66/134頁(yè) |
| 文件大小： | 2440K |
| 代理商： | MC68HC05JB4DW |
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February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
INTERRUPTS
REV 2
IRQE — IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF ag bit to initiate an IRQ interrupt
sequence.
1 =
Enables IRQ interrupt, that is, the IRQF ag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 =
The IRQF ag bit cannot generate an interrupt sequence.
IRQ2R — IRQ2 Interrupt Acknowledge
The IRQ2R acknowledge bit clears an IRQ2 interrupt by clearing the IRQ2 latch.
The IRQ2R acknowledge bit will always read as a logic zero.
1 =
Writing a logic one to the IRQ2R acknowledge bit will clear the IRQ2
latch.
0 =
Writing a logic zero to the IRQ2R acknowledge bit will have no effect
on the IRQ2 latch.
IRQ2F — IRQ2 Interrupt Request Flag
Writing to the IRQ2F ag bit will have no effect on it. If the additional setting of
IRQ2F ag bit is not cleared in the IRQ2 service routine and the IRQ2E enable bit
remains set the CPU will re-enter the IRQ2 interrupt sequence continuously until
either the IRQ2F ag bit or the IRQ2E enable bit is clear. The IRQ2F latch is
cleared by reset.
1 =
Indicates that an IRQ2 request is pending.
0 =
Indicates that no IRQ2 request triggered by pins PA4. The IRQ2F
ag bit can be cleared by writing a logic one to the IRQ2R
acknowledge bit to clear the IRQ2 latch.
IRQ2E - IRQ2 Interrupt Enable
The IRQ2E bit enables/disables the IRQ2F ag bit to initiate an IRQ2 interrupt
sequence.
1 =
Enables IRQ2 interrupt, that is, the IRQ2F ag bit can generate an
interrupt sequence. Reset clears the IRQ2E enable bit.
0 =
The IRQ2F ag bit cannot generate an interrupt sequence.
4.5.4 Port A External Interrupts (PA0-PA3, by mask option)
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins
if enabled by a single mask option. If enabled, the lower four bits of Port A can
activate the IRQ interrupt function, and the interrupt operation will be the same as
for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these
input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins
must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt
sources are also controlled by the IRQE enable bit.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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