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| 型號(hào)： | MC68HC05JB4DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 123/134頁(yè) |
| 文件大?。?/td> | 2440K |
| 代理商： | MC68HC05JB4DW |
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February 24, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05JB4
UNIVERSAL SERIAL BUS MODULE
REV 2
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. Reset clears this bit.
1 =
DATA1 Token active for next Endpoint 1/Endpoint 2 transmit
0 =
DATA0 Token active for next Endpoint 1/Endpoint 2 transmit
ENDADD — Endpoint Address Select
This
read/write
bit
species
whether
the
data
inside
the
registers
UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are satised
(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit
is congured for Endpoint 1, the USB responds with a NAK handshake packet.
1 =
The data buffers are used for Endpoint 2
0 =
The data buffers are used for Endpoint 1
TX1E — Endpoint 1/Endpoint 2 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.
Software should set the TX1E bit when data is ready to be transmitted. It must
be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake
to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
1 =
Data is ready to be sent.
0 =
Data is not ready. Respond with NAK.
FRESUM — Force Resume
This read/write bit forces a resume state (“K” or non-idle state) onto the USB
data lines to initiate a remote wake-up. Software should control the timing of the
forced resume to be between 10ms and 15 ms. Setting this bit will not cause
the RESUMF bit to set.
1 =
Force data lines to “K” state
0 =
Default
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
10.5.6 USB Control Register 2 (UCR2)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR2
R
0
TX1ST
0
ENABLE2 ENABLE1
STALL2
STALL1
$0037
W
TX1STR
reset
:
-
0
-
0000
= Unimplemented
Figure 10-25. USB Control Register 2 (UCR2)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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