參數(shù)資料
型號： MC68HC05JB4DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 127/134頁
文件大?。?/td> 2440K
代理商： MC68HC05JB4DW
GENERAL RELEASE SPECIFICATION
February 24, 1999
UNIVERSAL SERIAL BUS MODULE
REV
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff-
ers are shared by Endpoints 1 and 2 and depend on proper conguration of the
ENDADD bit.
10.6
USB INTERRUPTS
The USB module is capable of generating interrupts and causing the CPU to
execute the USB interrupt service routine. There are three types of USB
interrupts:
End of Transaction interrupts signify a completed transaction (receive or
transmit)
Resume interrupts signify that the USB bus is reactivated after having
been suspended
End of Packet interrupts signify that a low speed end of packet signal
was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for
determining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,
Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of
transaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module will
generate an interrupt by setting the RXD0F ag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the owchart of
SETUP transactions cannot be stalled by the USB function. A SETUP received by
a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE1D0
R
$0028
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
to
::::::::
UE1D7
R
$002F
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
reset:
XXXXXXXX
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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