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| 型號(hào)： | MC68HC05JB4DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 65/134頁 |
| 文件大小： | 2440K |
| 代理商： | MC68HC05JB4DW |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
INTERRUPTS
REV
Figure 4-4. External Interrupt (IRQ2) Logic
4.5.3 IRQ Control/Status Register (ICSR) - $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
IRQR — IRQ Interrupt Acknowledge
The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.
The IRQR acknowledge bit will always read as a logic zero.
1 =
Writing a logic one to the IRQR acknowledge bit will clear the IRQ
latch.
0 =
Writing a logic zero to the IRQR acknowledge bit will have no effect
on the IRQ latch.
IRQF — IRQ Interrupt Request Flag
Writing to the IRQF ag bit will have no effect on it. If the additional setting of
IRQF ag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF ag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
1 =
Indicates that an IRQ request is pending.
0 =
Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF ag bit can be cleared by writing a logic one to
the IRQR acknowledge bit to clear the IRQ latch and also
conditioning the external IRQ sources to be inactive (if the level
sensitive interrupts are enabled via mask option). Doing so before
exiting the service routine will mask out additional occurrences of
the IRQF.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICSR
R
IRQE
IRQ2E
0
IRQF
IRQ2F
0
$000A
W
IRQR
IRQ2R
reset:
10000000
Figure 4-5. IRQ Control and Status Register (ICSR)
IRQ2
LATCH
VDD
IRQ2
INTERRUPT
R
IRQ2E
IRQ2R
ICSR ($0A)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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