參數(shù)資料
型號(hào): MC68HC05P18A
廠商: Motorola, Inc.
英文描述: Low Cost HCMOS Microcontroller(低成本、8位HCMOS微控制器)
中文描述: 低成本HCMOS微控制器(低成本,8位HCMOS微控制器)
文件頁(yè)數(shù): 67/130頁(yè)
文件大?。?/td> 1200K
代理商: MC68HC05P18A
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16-Bit Timer
Timer
MC68HC05P18A
Technical Data
MOTOROLA
16-Bit Timer
67
L
G
R
of missing timer overflow interrupts due to clearing of the TOF. See
Figure 8-4
.
The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Since the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in the timer
status register (TSR) is set. An interrupt can also be enabled when
counter rollover occurs by setting the timer overflow interrupt enable bit
(TOIE) in the timer control register (TCR). See
Figure 8-5
.
Figure 8-4. State Timing Diagram for Timer Overflow
Figure 8-5. State Timing Diagram for Timer Reset
$FFFE
$FFFF
$0000
$0001
$0002
16-BIT FREE-RUNNING
COUNTER
TIMER OVERFLOW
FLAG (TOF)
PH2 CLOCK
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer
status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register
pair (TCRL).
Note: The counter and control registers are the only 16-bit timer registers affected by reset.
PH2 CLOCK
INTERNAL RESET
16-BIT FREE-RUNNING
COUNTER
RESET
(EXTERNAL OR OTHER)
$FFFC
$FFFD
$FFFE
$FFFF
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