參數(shù)資料
型號: MC68HC05P18A
廠商: Motorola, Inc.
英文描述: Low Cost HCMOS Microcontroller(低成本、8位HCMOS微控制器)
中文描述: 低成本HCMOS微控制器(低成本,8位HCMOS微控制器)
文件頁數(shù): 73/130頁
文件大小: 1200K
代理商: MC68HC05P18A
16-Bit Timer
Timer Status Register
MC68HC05P18A
Technical Data
MOTOROLA
16-Bit Timer
73
L
G
R
OLVL — Output Compare Output Level Select Bit
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
8.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts (see
Figure 8-11
). The only
remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measureanelapsedtime.Iftheproperprecautionsarenotdesignedinto
the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:
1.
The TSR is read when bit 5 (TOF) is set.
2.
The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
Address:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ICF
OCF
TOF
0
0
0
0
0
Write:
Reset:
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-11. Timer Status Register (TSR)
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