參數(shù)資料
型號(hào): MC68HC05P18A
廠(chǎng)商: Motorola, Inc.
英文描述: Low Cost HCMOS Microcontroller(低成本、8位HCMOS微控制器)
中文描述: 低成本HCMOS微控制器(低成本,8位HCMOS微控制器)
文件頁(yè)數(shù): 69/130頁(yè)
文件大?。?/td> 1200K
代理商: MC68HC05P18A
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16-Bit Timer
Output Compare
MC68HC05P18A
Technical Data
MOTOROLA
16-Bit Timer
69
L
G
R
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
1.
Block interrupts by setting the I bit in the condition code register
(CCR).
2.
Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3.
Read the timer status register (TSR) to arm the output compare
flag (OCF).
4.
Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag and
interrupt.
5.
Unblock interrupts by clearing the I bit in the CCR.
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in
Figure 8-7
.
9B
B6
BE
B7
B6
BF
Figure 8-7. Output Compare Software Initialization Example
XX
XX
16
13
17
SEI
LDA
LDX
STA
LDA
STX
DATAH
DATAL
OCRH
TSR
OCRL
BLOCK INTERRUPTS
HI BYTE FOR COMPARE
LOW BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
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