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參數(shù)資料
| 型號(hào)： | MC68HC05P18MDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 102/144頁(yè) |
| 文件大?。?/td> | 1348K |
| 代理商： | MC68HC05P18MDW |
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Advance Information
MC68HC(8)05P18 — Rev. 2.0
60
Operating Modes
MOTOROLA
Operating Modes
6.5.2 Halt Mode
Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode (both halt and wait modes consume more power
than stop mode).
In halt mode the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
halt mode and resume normal operation. Halt mode also can be exited
when an IRQ external interrupt (or port A, if selected as an option in the
MOR2) or external RESET occurs. When exiting halt mode, the PH2
clock will resume after a delay of one to 4064 PH2 clock cycles. This
varied delay time is the result of the halt mode exit circuitry testing the
oscillator stabilization delay timer (a feature of the stop mode), which has
been free-running (a feature of the wait mode).
NOTE:
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently.
6.5.3 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05P1A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05P1CDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05P1CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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