參數(shù)資料
型號: MC68HC05P18MDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 26/144頁
文件大?。?/td> 1348K
代理商: MC68HC05P18MDW
Instruction Set
Opcode Map
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
Instruction Set
121
12.6 Opcode Map
The opcode map is provided in Table 12-7.
TAX
Transfer
Accumulator to Index
Register
X
← (A)
—————
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for
Negative or Zero
(M) – $00
—————
DIR
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
5
4
TXA
Transfer Index
Register to
Accumulator
A
← (X)
—————
INH
9F
2
WAIT
Stop CPU Clock and
Enable
Interrupts
— — — —
INH
8F
2
A
Accumulator
opr
Operand (one or two bytes)
C
Carry/borrow flag
PC
Program counter
CCR
Condition code register
PCH
Program counter high byte
dd
Direct address of operand
PCL
Program counter low byte
dd rr
Direct address of operand and relative offset of branch instruction
REL
Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
rr
Relative program counter offset byte
EXT
Extended addressing mode
SP
Stack pointer
ff
Offset byte in indexed, 8-bit offset addressing
X
Index register
H
Half-carry flag
Z
Zero flag
hh ll
High and low bytes of operand address in extended addressing
#
Immediate value
I
Interrupt mask
Logical AND
ii
Immediate operand byte
Logical OR
IMM
Immediate addressing mode
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
–( )
Negation (two’s complement)
IX1
Indexed, 8-bit offset addressing mode
Loaded with
IX2
Indexed, 16-bit offset addressing mode
?
If
M
Memory location
:
Concatenated with
N
Negative flag
Set or cleared
n
Any bit
Not affected
Table 12-6. Instruction Set Summary (Sheet 7 of 7)
Source
Form
Operation
Description
Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HIN Z C
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